This application claims the priority benefit of Taiwan application serial no. 91209350, filed Jun. 21, 2002.
1. Field of the Invention
The present invention is generally related to a flip-chip package substrate, and particularly to a flip-chip package substrate for reducing plane inductance.
2. Description of Related Art
Flip-chip interconnect technique utilizes an area array to distribute the die pads on the active surface of the die and forms bumps on the die pads. The die is afterwards flipped where the bumps on the die are connected to the contacts of a carrier for external electrical connection. The widespread popularity of flip-chip interconnect method for chip packaging is recognized by its ability to accommodate high pin count packages and the advantage of shrinking the overall package size and shortening the signal transmission paths. The common flip-chip interconnect methods include flip-chip ball grid array (FCBGA), flip-chip pin grid array (FCPGA), and chip on board (COB), and the like.
Please refer to FIG. 1, a conventional FCBGA package structure is shown. A die 10 is provided with a plurality of die pads 14 on the active surface for providing an interface for signal input/output. A plurality of bumps 20 located on die pads 14 are electrically connected to the bump pads 33a of chip package substrate 30. Chip package substrate 30 is formed by alternating a plurality of wiring layers 32 and insulation layers 34, wherein two or more wiring layers 32 are connected by conductive plugs 36 which penetrate insulation layers 34, wherein conductive plugs 36 comprise plating through hole (PTH) 36a and conductive plugs 36b. Furthermore, the bump pads 33a at the uppermost of chip package substrate 30 are formed by the wiring layer 32a which is located at the uppermost of the chip package substrate 30. A patterned solder mask 38a is deposited over wiring layer 32a for protection but exposing bump pads 33a. 
Please again refer to FIG. 1, a plurality of bonding pads 33b located on the opposite bottommost of chip package substrate 30 are formed by the wiring layer 32b located at the bottommost of the chip package substrate 30 where a patterned solder mask 38b is deposited over wiring layer 32b for protection but exposing bonding pads 33b. Balls and others electrical structures of the like can be connected to bonding pads 33b for providing further electrical connections. As a result, die pads 14 of die 10 are electrically and mechanically connected to bump pads 33a of the chip package substrate 30 by bumps 20, and further electrically connect down to bonding pads 33b on the bottom of chip package substrate 30 by conductive plugs 36 and wiring layers 32. Bonding pads 33b are further connected to balls 40 for providing electrical and mechanical connection to the next level electrical device such as a printed circuit board (PCB).
Please continue to refer to FIG. 1, due to die pads 14 of die 10 are distributed on the active surface 12 in the form of an area array, bump pads 33a also have to be arranged in the form of an area array on the uppermost layer of chip package substrate 30. Furthermore, bump pads 33a comprise a variety of bump pads of different purposes such as signal bump pads, power bump pads, and ground bump pads, core power/ground bump pads to correspond to the different functions of die pads 14 of die 10.
Please simultaneously refer to FIGS. 1 and 2A, FIG. 2A is a schematic diagram of a conventional layout of the bump pads of a chip package substrate. The conventional layout of bump pads 33a is designed according to the function of bump pads 33a. A core power/ground bump pad 33a is located in the center forming a core power/ground region 110. Surrounding the core power/ground region 110 arc different rings of signal, power, and power-to-ground bump pads located adjacent to one another in the shape of a closed ring. A first ring of signal bump pads 120 is formed at the periphery of core power/ground region 110, then a ring of power bump pads 130 at a more outwards periphery, followed by a ring of ground bump pads 140 at an even more outwards periphery, and finally a second ring of signal bump pads 150 located at the most outwards periphery. Furthermore, power bump pads ring 130 further has multiple power bump pads regions 130a, 130b, 130c, and 130d, wherein the first and the last bump pads regions are neighbors because of the ring arrangement. These power bump pads regions 130a, 130b, 130c, and 130d are each a separate power group.
Please simultaneously refer to FIGS. 1 and 2B, FIG. 2B is a schematic diagram of the connection layout of a conventional chip package substrate. For coherence with the bump pads layout in FIG. 2, prior art provides a corresponding bonding pads layout suitable for a chip package substrate for reducing the routing path and plane inductance. A core power/ground region 112 is formed by locating the die pads 33b with core power/ground function in the center of chip package substrate 30. Extending outwards to the periphery of chip package substrate 30 from the core power/ground region 112 is a first signal bump pads coil 122, a power bump pads coil 132, a ground bump pads coil 142, and a second signal bump pads coil 152 at the most outwards periphery. Furthermore, power bump pads ring 132 farther has multiple power bump pads regions 132a, 132b, 132c, and 132d, wherein the first and the last bump pads regions are neighbors because of the ring arrangement. These power bump pads regions 132a, 132b, 132c, and 132d are each a separate power group.
Please refer to FIGS. 1 and 3, FIG. 3 is a schematic diagram of the connection between the external bump pads and balls of a power group. A power group 101 electrically connects through to ball 102 by wiring layers 32 and conductive plugs 36 of chip package substrate 30. Therefore within two ends (as illustrated in circles) of the same power group, a phenomenon known as plane inductance occurs which affects the electrical properties of die 10 after packaging.
The present invention provides a chip packaging substrate that reduces the effect of plane inductance at two ends of the same power group and effectively limits the amount of synchronous switching noise (SSN) to further increase the electrical properties of the die after packaging.
Improving according to the above purposes, the present invention provides a chip package substrate with a plurality of wiring layers alternating stacked between at least one insulation layer separating the two wiring layers. A plurality of conductive plugs that penetrate the insulation layers provides electrical connection between the separated wiring layers. The uppermost wiring layer further comprises at least one power bump pads region with a plurality of power bump pads, and the bottommost wiring layer further comprises a plurality of power bonding pads. These power bump pads regions can interchange with the neighboring ground bump pads regions, or the ends of the power bump pads regions can extend towards the ground bump pads regions, so the power bump pads on both ends of the power bump pads region can respectively electrically connect to the bonding pads by the wiring layers and conductive plugs.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.